This application is based on an application No. 2002-25146 filed in Japan, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular relates to techniques for reducing the current consumption of a semiconductor memory device that has a read circuit including a step-up power supply.
2. Prior Art
The following method is typically used to read information from a semiconductor memory device equipped in a microcomputer. One of a plurality of memory cells arranged in the form of a matrix is selected by a word line and a bit line, and stored information is sensed by a sense amplifier from a cell current of the selected memory cell. To supply power to the internal circuitry of such a semiconductor memory device, a step-up power supply that steps up an externally-supplied voltage may be equipped in the semiconductor memory device (e.g. Unexamined Japanese Patent Application Publication No. H10-302492).
FIG. 1 shows a construction of a conventional semiconductor memory device that includes a step-up power supply.
In the drawing, a microcomputer 130 is roughly made up of a CPU 121 which controls the overall microcomputer 130, and a semiconductor memory device 120.
The semiconductor memory device 120 includes a step-up power supply 113, a memory array 7, word lines 111, a row decoder 6, bit lines 112, a column decoder 8, a sense amplifier 9, a data latch 110, and a pulse generator 5.
The memory array 7 is made up of a plurality of memory cells which are arranged in the form of a matrix. Each memory cell stores one-bit information.
The word lines 111 are arranged in a Y direction of the memory array 7.
The row decoder 6 selects one of the word lines 111 using voltage Vg supplied from the step-up power supply 113 and address information AddY given from the CPU 121.
The bit lines 112 are arranged in an X direction of the memory array 7.
The column decoder 8 selects one of the bit lines 112 using address information AddX given from the CPU 121.
The sense amplifier 9 reads one-bit information from a memory cell selected by the row decoder 6 and the column decoder 8.
The data latch 110 latches the data read by the sense amplifier 9.
The pulse generator 5 controls the sense amplifier 9 using signals (SLOW and NDS) from the CPU 121.
The step-up power supply 113 includes a reference voltage generator 1, a step-up pump 2, a Vp detector 3, and a differential amplifier 4.
The reference voltage generator 1 generates reference voltage VREF.
The step-up pump 2 generates voltage Vp higher than power supply voltage VDD which is supplied from outside.
The Vp detector 3 controls the step-up pump 2 in accordance with comparison between reference voltage VREF generated by the reference voltage generator 1 and voltage Vp generated by the step-up pump 2.
The differential amplifier 4 generates voltage Vg that is double the level of reference voltage VREF, using voltage Vp.
In such a construction, a read is performed as follows. When address information AddX and AddY are input respectively to the column decoder 8 and the row decoder 6, the row decoder 6 selects one word line 111 according to address information AddY, whereas the column decoder 8 selects one bit line 112 according to address information AddX. The sense amplifier 9 senses the storage contents of a memory cell selected by the word line 111 and the bit line 112, and outputs signal DOUT which is high or low depending on the storage contents. The data latch 110 latches DOUT and outputs the data.
When such a read is performed with a long cycle of several microseconds, usually the sense amplifier 9 is activated only while information is being read from the memory array 7, to reduce current consumption. On the other hand, the step-up power supply 113 constantly generates voltage Vg to guarantee normal read operations.
FIG. 2 shows an operation sequence of the semiconductor memory device 120, when a read is performed with a long cycle.
At time T2, read control signal NDS output from the CPU 121 makes a high to low transition. This causes output SAAV of the pulse generator 5 to transition from low to high. As a result, the sense amplifier 9 which receives SAAV is activated The sense amplifier 9 reads information stored in a selected memory cell, and outputs it as DOUT. At time T3, the pulse generator 5 changes SAAV from high to low. At this point, the data latch 110 latches DOUT, and keeps outputting the data until latching in the next cycle. The sense amplifier 9 is deactivated when SAAV becomes low at time T3.
In the meantime, voltage Vg is steadily generated by the reference voltage generator land the differential amplifier 4. On the other hand, voltage Vp generated by the step-up pump 2 has a waveform with some width, since the step-up pump 2 is activated/deactivated by the Vp detector 3 depending on detection of voltage Vp.
When a read is performed with a long cycle, the sense amplifier 9 is activated only while information is actually being read from the memory array 7, and deactivated once the information has been read and latched. This contributes to a lower current consumption, when compared with the case where the sense amplifier 9 is active during the whole cycle.
Meanwhile, the step-up power supply 113 is active and generates voltage Vg during the whole cycle, as explained earlier. This causes unnecessary current consumption. Given that the step-up power supply 113 consumes a large amount of current, such unnecessary current consumption need be addressed.
The present invention was conceived in view of the problem described above, and has an object of providing a semiconductor memory device in which the current consumption of a read circuit including a step-up power supply is reduced when compared with conventional semiconductor memory devices.
The stated object can be achieved by a semiconductor memory device having a memory array, including: a read unit operable to read information stored in a memory cell in the memory array; a step-up unit operable to step up a voltage supplied from outside the semiconductor memory device, and supply the stepped-up voltage to the memory cell; a start control unit operable to have the step-up unit start the stepping up after a read cycle begins; a detection unit operable to detect that the stepped-up voltage has reached a predetermined level required for the read unit to read the information from the memory cell, and have the read unit start the reading upon the detection; and a stop control unit operable to have the step-up unit stop the stepping up, when a predetermined time period required for the read unit to complete the reading has elapsed since the detection.
It should be noted here that the step-up unit does not step up the voltage to the predetermined level instantly. Rather, after the start control unit has the step-up unit start the step up, the step-up unit steps up the voltage with time, as a result of which the voltage reaches the predetermined level. The predetermined level here is higher than a power supply voltage supplied from outside, and is a multiple of the reference voltage as one example. The detection by the detection unit is carried out, for example, by comparing a submultiple of the stepped-up voltage (i.e. a voltage obtained by stepping down the stepped-up voltage by means of resistance voltage division) with a constant voltage lower than the power supply voltage.
According to the above construction, the semiconductor memory device starts stepping up the voltage to be supplied to the memory cell, after the read cycle begins. Once the voltage has reached the predetermined level, the actual read operation is launched. The semiconductor memory device stops stepping up the voltage when the predetermined time period has elapsed since the read operation is launched. The predetermined time period here is a time period necessary for the read unit to perform the actual read operation. Thus, the time during which the voltage to be supplied to the memory cell is stepped up is minimized in association with the time taken for the read operation. This contributes to a lower current consumption, when compared with the case where the time during which the voltage is stepped up is unnecessarily long. Especially if the read cycle is relatively long such as several microseconds or more, the time during which the read operation is not performed is longer than the time during which the read operation is performed, within the read cycle. In such a case, if the step up is constantly performed throughout the read cycle, a current is unnecessarily consumed in a long period during which the read operation is not performed. According to the present invention, however, the step up is started little before the actual read operation is launched, and stopped at the same time as the completion of the read operation. This eliminates unnecessarily current consumption in the time during which the read operation is not performed.
Here, the read unit may include: a sense amplifier operable to amplify a cell current of the memory cell and output the amplified cell current, wherein the step-up unit includes: a reference voltage generator operable to generate a constant reference voltage which is no higher than a power supply voltage supplied from outside the semiconductor memory device; a step-up pump operable to generate a first voltage which is higher than the power supply voltage; a differential amplifier operable to generate a second voltage using the first voltage and supply the second voltage to the memory cell, the second voltage increasing with time to the predetermined level that is a predetermined multiple of the reference voltage and is higher than the power supply voltage; and a first voltage detector operable to have the first voltage stay within a fixed range, by comparing the first voltage with the second voltage and activating/deactivating the step-up pump depending on a result of the comparison, wherein the detection unit includes: a second voltage detector operable to (a) detect that the second voltage has reached the predetermined level, by comparing a comparative voltage obtained by stepping down the second voltage with the reference voltage, and (b) activate the sense amplifier upon the detection, the start control unit activates the differential amplifier and the first voltage detector to have the step-up unit start the stepping up, and further activates the second voltage detector, after the read cycle begins, and the stop control unit deactivates the step-up pump, the differential amplifier, and the first voltage detector to have the step-up unit stop the stepping up, and further deactivates the second voltage detector, when the predetermined time period has elapsed since the activation of the sense amplifier.
This construction corresponds to the semiconductor memory device 200 shown in FIG. 3. In detail, the step-up unit corresponds to the step-up power supply 201, the reference voltage generator corresponds to the reference voltage generator 1, the step-up pump corresponds to the step-up pump 2, the differential amplifier corresponds to the differential amplifier 100, the first voltage detector corresponds to the Vp detector 3, the second voltage detector corresponds to the Vg detector 11, and the start control unit and the stop control unit correspond to the control circuit 105.
Here, the semiconductor memory device may further include: a sense amplifier deactivator operable to deactivate the sense amplifier, when the predetermined time period has elapsed since the activation of the sense amplifier; and a sense amplifier output latch operable to hold the output of the sense amplifier for a fixed time period after the deactivation of the sense amplifier.
In a semiconductor memory device, a step-up pump has the largest power consumption, and a sense amplifier has the second largest power consumption. Accordingly, by deactivating the sense amplifier along with the step-up unit including the step-up pump when the read operation ends, power consumption is further reduced. In this case, to obtain the output of the sense amplifier even after the sense amplifier is deactivated, the sense amplifier output latch is equipped in the semiconductor memory device.
Here, the second voltage detector may output a predetermined signal to activate the sense amplifier, wherein the semiconductor memory device further include: a sense amplifier activation signal latch operable to hold the predetermined signal output from the second voltage detector for a set time period, and output the held signal to the sense amplifier.
The second voltage detector outputs the predetermined signal upon detecting that the second voltage generated by the differential amplifier has reached the targeted level. Upon receiving this signal, the sense amplifier is activated. Here, the sense amplifier activation signal latch for latching the signal output from the second voltage detector is equipped in the semiconductor memory device. By activating the sense amplifier according to the output of this latch, even if noise acts upon the output of the differential amplifier and as a result the output of the second voltage detector oscillates, the sense amplifier can operate stably without being affected by such an oscillation. In this way, a malfunction caused by the occurrence of noise affecting the stepped-up voltage is prevented, with it being possible to realize stable read operations.
Here, the differential amplifier may include: a first n-channel transistor operable to make the comparative voltage which is obtained by dividing the second voltage using a resistance voltage divider, equal to the second voltage upon the deactivation of the differential amplifier; a second n-channel transistor operable to interrupt a flow of current through a differential circuit portion of the differential amplifier, upon the deactivation of the differential amplifier; and a p-channel transistor having a gate connected to a node on which the second voltage is provided, and operable to short-circuit the node and the step-up pump upon the deactivation of the differential amplifier.
This construction corresponds to the stop circuit 300 shown in FIG. 6. In detail, the first n-channel transistor corresponds to the n-channel transistor 25, the second n-channel transistor corresponds to the n-channel transistor 23, and the p-channel transistor corresponds to the p-channel transistor 22.
According to this construction, when the differential amplifier is deactivated, an intermediate node potential is set in anticipation of a change which may occur next time the differential amplifier is activated. This keeps the second voltage generated by the differential amplifier from unwantedly exceeding the targeted level upon the activation of the differential amplifier, with it being possible to ensure the stable operation of the differential amplifier.
Here, the differential amplifier may include: a plurality of charge supply p-channel transistors each operable to supply a charge generated by the step-up pump to the differential amplifier; and a conduction control p-channel transistor connected in series to at least one charge supply p-channel transistor out of the plurality of charge supply p-channel transistors, and operable to bring the charge supply p-channel transistor into or out of conduction depending on a read mode.
This construction corresponds to the switch circuit 301 shown in FIG. 6. In detail, the plurality of charge supply p-channel transistors correspond to the p-channel transistors 16 and 17, and the conduction control p-channel transistor corresponds to the p-channel transistor 24.
According to this construction, when the read mode is a high-speed mode with a read cycle of several tens of nanoseconds, all of the charge supply p-channel transistors are used to enhance the charge supply capability and suppress a voltage drop by a load circuit. When the read mode is a low-speed mode with a read cycle of several tens of microseconds, on the other hand, only part of the charge supply p-channel transistors is used to lower the charge supply capability, thereby preventing an overshoot of unwantedly exceeding the targeted level. In this way, the voltage can be generated stably in both the high-speed mode and the low-speed mode.
Here, the second voltage detector may include: a differential circuit portion including a first p-channel transistor and a second p-channel transistor which are current-mirror connected; a third p-channel transistor connected in parallel with the first p-channel transistor which has a gate and a drain connected, and operable to short-circuit the drain of the first p-channel transistor and an output of the power supply voltage upon the deactivation of the second voltage detector; a first n-channel transistor connected with the second p-channel transistor, and operable to ground a drain of the second p-channel transistor upon the deactivation of the second voltage detector; a second n-channel transistor operable to interrupt a flow of current through the differential circuit portion upon the deactivation of the second voltage detector; a fourth p-channel transistor connected with a node on which the second voltage is provided, and operable to change the comparative voltage which is obtained by dividing the second voltage using a resistance voltage divider, to a ground voltage upon the deactivation of the second voltage detector; a third n-channel transistor and a fifth p-channel transistor connected in series with each other, and operable to convert an output of the differential circuit portion to a logic signal; and a cutoff unit operable to bring the third n-channel transistor out of conduction upon the deactivation of the second voltage detector.
This construction corresponds to the stop circuit 401 shown in FIG. 8. In detail, the first p-channel transistor and the second p-channel transistor correspond to the two p-channel transistors 30, the third p-channel transistor corresponds to the p-channel transistor 37, the first n-channel transistor corresponds to the n-channel transistor 36, the second n-channel transistor corresponds to the n-channel transistor 33, the fourth p-channel transistor corresponds to the p-channel transistor 39, the fifth p-channel transistor corresponds to the p-channel transistor 38, and the third n-channel transistor corresponds to the n-channel transistor 40.
According to this construction, when the second voltage detector is deactivated, an intermediate node potential is set in anticipation of a change which may occur next time the second voltage detector is activated. This keeps the second voltage detector from wrongly outputting a detection signal upon the activation. Hence the stable operation of the second voltage detector is ensured.
Here, the second voltage detector may include: a first n-channel transistor having a gate which receives the comparative voltage obtained by dividing the second voltage using a resistance voltage divider; a second n-channel transistor having a gate which receives the reference voltage; and a third n-channel transistor connected in parallel with the first n-channel transistor so that a total capability of the first n-channel transistor connected with the third n-channel transistor is greater than a capability of the second n-channel transistor.
According to this construction, even when the second voltage generated by the differential amplifier is stabilized at a level slightly lower than the targeted level, the second voltage detector is kept from a malfunction of not outputting a detection signal permanently. Hence the normal operation of the second voltage detector is ensured.
Here, the semiconductor memory device may further include: a transistor diode-connected with a node on which the first voltage is provided, and operable to supply a charge from an external power supply to the node if the node falls below the power supply voltage after the deactivation of the step-up pump.
According to this construction, the first voltage at the node corresponding to the output of the step-up pump decreases in a high impedance state due to a leakage of current, but does not fall below VDD-Vt. As a result, the step up in the next read cycle can be started not from a ground level but from VDD-Vt, which contributes to a lower current consumption when compared with the case where the step up is started from a ground level.
Here, the semiconductor memory device may further include: a transistor diode-connected with a node on which the second voltage is provided, and operable to supply a charge from an external power supply to the node if the node falls below the power supply voltage after the deactivation of the differential amplifier.
According to this construction, the second voltage at the node corresponding to the output of the differential amplifier decreases in a high impedance state due to a leakage of current, but does not fall below VDD-Vt. As a result, the step up in the next read cycle can be started not from a ground level but from VDD-Vt, which contributes to a lower current consumption when compared with the case where the step up is started from a ground level.